Design and Analysis of Low Power Multipliers and 4:2 Compressor Using Adiabatic Logic

For high speed applications, a huge number of adders or compressors are to be used in multiplications to perform the partial product addition. In this paper a new approach of reducing power for a given system is developed that is adiabatic logic. The Array multiplier, Vedic 4x4 multiplier and 8x8 multiplier are designed using energy recovery logic in the inverter. The number of adders is reduced by introducing special kind of adders that are capable to add five/six/seven bits per decade. These adders are called compressors. A 4:2 compressor is developed using adiabatic logic for multiplier in order to reduce the power with facilitation of low power logic technique. The Vedic multiplier is designed using the compressor and the power results are obtained using TANNER EDA 12.0 tool. This paper presents a novel scheme for analysis of low power multipliers using adiabatic logic in inverter and in the compressor. KeywordsAdiabatic logic, Compressor, Multipliers.